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VS1103b Datasheet

VS1103B REGISTERS

8.11

UART (Universal Asynchronous Receiver / Transmitter)

The RS232 UART implements a serial interface using RS232 standard 8N1 (8 data bits, no

parity, 1 stop bit).

Start

bit

Stop

bit

Figure 15: RS232 Serial Interface Protocol

When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission

begins with a start bit (logic zero) and continues with data bits (LSB ﬁrst) and ends up with a

stop bit (logic high). 10 bits are sent for each 8-bit byte frame.

8.11.1

Registers

UART registers, preﬁx UARTx_

Reg

Type

Reset

Abbrev

Description

0xC028

STATUS[3:0]

Status

0xC029

r/w

DATA[7:0]

Data

0xC02A

r/w

DATAH[15:8]

Data High

0xC02B

r/w

DIV

Divider

8.11.2

Status UARTx_STATUS

A read from the status register returns the transmitter and receiver states.

UARTx_STATUS Bits

Name

Bits

Description

UART_ST_RXORUN

Receiver overrun

UART_ST_RXFULL

Receiver data register full

UART_ST_TXFULL

Transmitter data register full

UART_ST_TXRUNNING

Transmitter running

UART_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from

the receiver shift register to the data register, otherwise it is cleared.

UART_ST_RXFULL is set if there is unread data in the data register.

UART_ST_TXFULL is set if a write to the data register is not allowed (data register full).

UART_ST_TXRUNNING is set if the transmitter shift register is in operation.

8.11.3

Data UARTx_DATA

A read from UARTx_DATA returns the received byte in bits 7:0, bits 15:8 are returned as ’0’. If

there is no more data to be read, the receiver data register full indicator will be cleared.

Version: 1.04, 2018-03-16

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