VS1103 datasheet(52/61 Pages) VLSI

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VS1103b Datasheet

VS1103B REGISTERS

A receive interrupt will be generated when a byte is moved from the receiver shift register to

the receiver data register.

A write to UARTx_DATA sets a byte for transmission. The data is taken from bits 7:0, other

bits in the written value are ignored. If the transmitter is idle, the byte is immediately moved

to the transmitter shift register, a transmit interrupt request is generated, and transmission is

started. If the transmitter is busy, the UART_ST_TXFULL will be set and the byte remains in the

transmitter data register until the previous byte has been sent and transmission can proceed.

8.11.4

Data High UARTx_DATAH

The same as UARTx_DATA, except that bits 15:8 are used.

8.11.5

Divider UARTx_DIV

UARTx_DIV Bits

Name

Bits

Description

UART_DIV_D1

15:8

Divider 1 (0..255)

UART_DIV_D2

7:0

Divider 2 (6..255)

The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending

on the master clock frequency to get the correct bit speed. The second divider (D2) must be

from 6 to 255.

The communication speed f =

(D1+1)×(D2) , where

fm is the master clock frequency, and f is

the TX/RX speed in bps.

Divider values for common communication speeds at 26 MHz master clock:

Example UART Speeds, fm = 26M Hz

Comm. Speed [bps]

UART_DIV_D1

UART_DIV_D2

4800

9600

14400

19200

28800

38400

57600

226

115200

226

8.11.6

Interrupts and Operation

Transmitter operates as follows: After an 8-bit word is written to the transmit data register it will

be transmitted instantly if the transmitter is not busy transmitting the previous byte. When the

transmission begins a TX_INTR interrupt will be sent. Status bit [1] informs the transmitter data

new word must not be written to transmitter data register if it is not empty (bit [1] = ’0’). The

Version: 1.04, 2018-03-16

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