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VS1103 Datasheet(PDF) 29 Page - VLSI Solution Oy

Part # VS1103
Description  VS1103b - MIDI/ADPCM AUDIO CODEC
PDF  61 Pages
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Manufacturer  VLSI [VLSI Solution Oy]
Direct Link  https://www.vlsi.fi/
Logo VLSI - VLSI Solution Oy

VS1103 Datasheet(HTML) 29 Page - VLSI Solution Oy

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VS1103b Datasheet
6
FUNCTIONAL DESCRIPTION
4 When mode register write specifies a software reset the worst-case time is 16600 XTALI
cycles.
5 Writing to this register may force internal clock to run at 1.0 × XTALI for a while. Thus it is not
a good idea to send SCI or SDI bits while this register update is in progress.
Note: it is not allowed to do an SCI operation while DREQ is low. If this is done, however,
DREQ stays low even after the SCI operation has been processed.
6.6.1
SCI_MODE (RW)
SCI_MODE is used to control the operation of VS1103b and defaults to 0x0800 (SM_SDINEW
set).
SCI_MODE bits
Name
Bit
Function
Value
Description
SM_DIFF
0
Differential
0
normal in-phase audio
1
left channel inverted
SM_RECORD_PATH
1
Choose ADPCM recording
0
A/D stream
path
1
Mixer output
SM_RESET
2
Soft reset
0
no reset
1
reset
SM_OUTOFMIDI
3
Cancel MIDI decoding
0
no
1
yes
SM_PDOWN
4
Powerdown
0
power on
1
powerdown
SM_TESTS
5
Allow SDI tests
0
not allowed
1
allowed
SM_ICONF
7:6
Input configuration
0
SDI MIDI, SCI ADPCM
1
SCI MIDI, SDI ADPCM
2
UART RT-MIDI, SCI ADPCM
3
UART RT-MIDI, SDI ADPCM
SM_DACT
8
DCLK active edge
0
rising
1
falling
SM_SDIORD
9
SDI bit order
0
MSb first
1
MSb last
SM_SDISHARE
10
Share SPI chip select
0
no
1
yes
SM_SDINEW
11
VS10xx native SPI modes
0
no
1
yes
SM_EARSPEAKER
13:12
Earspeaker setting
0
off
1
low
2
mid
3
high
SM_LINE_IN
14
A/D stream input
0
microphone
selector
1
line in
SM_ADPCM
15
ADPCM recording active
0
no
1
yes
When SM_DIFF is set, the player inverts the left channel output. For a stereo input this creates
virtual surround, and for a mono input this creates a differential left/right signal.
If SM_RECORD_PATH is set, ADPCM recording is performed from the A/D stream at 8 kHz,
otherwise the Mixer output is recorded at 44.1 kHz. This bit is only valid if SM_ADPCM is set.
Version: 1.04, 2018-03-16
29



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