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ATMU (Address Translation and Mapping Unit)

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-107

RapidIO read types and OCeaN write types can only map to RapidIO write types including

doorbells.

17.7.1.1 Outbound ATMU Bypass Mode

Note that some transactions may not require ATMU translation because the address associated

with the original transaction is already mapped to the appropriate address space. Although the

DMA controller can initiate outbound RapidIO transactions that may or may not bypass ATMU

translation, it is the only source of transactions that can bypass outbound ATMU translation. The

DMA controller may bypass ATMU translation for any outbound transaction that it supports.

17.7.1.2 Outbound Special Transactions and Requirements

Due to requirements of the Parallel RapidIO Interconnect Specification, I/O read home and flush

with data transactions require special handling. Outbound I/O read transactions cannot cross a

32-byte cache-line boundary and cannot be greater than 32 bytes in size because the RapidIO

interface requires wrapping around a 32-byte cache-line for I/O read home transactions. Therefore,

regardless of the size of the original request, the address for outbound I/O read transactions is

double-word aligned, and the size is set to 32 bytes in order to fetch an entire cache-line. There is

also a requirement for outbound requests originated by the PCI controller. These transactions must

map to an ATMU window in which the ROWARn specifies a transaction flow level of zero and

has the PCI bit set. This causes the outbound transaction to be sent through the RapidIO interface

with a priority of one because the transaction flow level is incremented when the PCI bit is set.

To comply with the Parallel RapidIO Interconnect Specification other transactions also have

special requirements. Outbound maintenance transactions, for example, may not exceed 64 bytes.

Also, outbound doorbells are generated through the ATMU by using write transactions whose

sizes are 2, 4 or 8 bytes and whose address is aligned to a doubleword boundary. A doorbell

generated using a 2-byte write gets its INFO field from the data associated with the write

transaction. A doorbell generated using a 4 or 8 byte write gets its INFO field from the

most-significant 2 bytes of the data associated with the write transaction.

Outbound swrite transactions must be at least a double word, and atomic transactions may only

request 1, 2, or 4 bytes. Furthermore, atomic transactions must meed the RapidIO alignment

requirements as specified in the Parallel RapidIO Interconnect Specification.

The Parallel RapidIO Interconnect Specification should be referenced for any additional

requirements that are not listed in this section.

17.7.2 Inbound ATMU Translation

Inbound ATMU windows perform the address translation from the 34-bit external RapidIO

address space to the 32-bit internal address space. Inbound ATMU windows also attach attributes,

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