MPC8540 datasheet(1032/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-108

Freescale Semiconductor

RapidIO Interface

transaction type, and the target interface to the transaction. The RapidIO controller has four

inbound ATMU windows plus the default window 0. The default window is always enabled.

Overlapping inbound window hits result in the use of the lowest number window register set hit.

17.7.2.1 Inbound ATMU LCSBA1CSR Window

There is an additional inbound window that is used for inbound translation. It is a special condition

for external accesses to LCSBA1CSR (local configuration space base address register) address

space. The purpose of the LCSBA1CSR window is to allow external devices to access the

LCSBA1CSR address space without knowledge of the internal memory map. When a remote

device attempts to access the LCSBA1CSR register set (address hitting LCSBA1CSR window),

the lower 20 bits are used as the offset to access the specific register in the LCSBA1CSR address

space. The LCSBA1CSR window has the highest priority for inbound translation. If the inbound

transaction’s address does not hit the LCSBA1CSR window or any of the four inbound ATMU

windows (1–4), the translation attributes defined by the default window (window 0) are used.

The LCSBA1CSR window does not have specific RIWBAR, RIWTAR or RIWAR registers.

However, for the purposes of translation, bits 1–14 of the LCSBA1CSR correspond to bits 10–23

of RIWBARn, and bits 12–23 of the CCSRBAR correspond to bits 12–23 of RIWTARn. The

hard-coded attributes for this window as they correspond to the RIWAR register fields are:

EN = 0b1, TGINT = 0b1111, RDTYP and WRTYP = 0b0100 and SIZE = 0b010011.

17.7.2.2 Inbound ATMU Bypass Mode

Just as some outbound transactions may bypass outbound ATMU translation, some inbound

transactions may also bypass ATMU translation because the address associated with the original

transaction is already mapped to the appropriate address space. Inbound messages, doorbells and

port-writes go through a different form of address mapping and are not mapped through the

ATMU. These transactions have the stash and cache_lock attributes cleared. Similarly, the

no_snoop bit is set according to the corresponding programming model of the specific transaction

type regardless of the value specified in the RIWAR of the selected ATMU window. For more

information about these transactions, see Section 17.8.4.1, “Data Message Controller,”

Section 17.8.4.4, “Doorbell Message Controller,” and Section 17.8.4.5, “Port-Write Controller

Structure.”

17.7.2.3 Inbound Special Transactions and Requirements

Just as with outbound translation, some inbound transactions require special handling to comply

with the Parallel RapidIO Interconnect Specification. For example, inbound I/O read home and

flush with data transactions require special handling. Snooping is enabled for these transactions

regardless of the no-snoop value specified in the RIWAR of the selected window. Furthermore,

these transactions should target local memory. Targeting any other interface is a programming

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