PCA9306DC1SLASHDG datasheet(13/38 Pages) NXP

13 / 38 page

NXP Semiconductors

PCA9306

Dual bidirectional I2C-bus and SMBus voltage-level translator

A description of the rise time applied to either An or Bn output going from LOW to HIGH

is as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B

sides are essentially one node. They will rise together with an RC time constant that is

the sum of all the capacitance from both sides and the parallel of the resistance from

both sides. As the signal approaches the VCC(A) voltage, the channel resistance goes up

and the waveforms separate, with the B side finishing its rise with the RC time constant

of the B side. The rise to VCC(A) is essentially the same for both sides.

There are some basic guidelines to follow that will help maximize the performance of the

device:

• Keep trace length to a minimum by placing the NVT device close to the processor.

• The signal round trip time on trace should be shorter than the rise or fall time of signal

to reduce reflections.

• The faster the edge of the signal, the higher the chance for ringing.

• The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher the

frequency the device can use.

The system designer must design the pull-up resistor value based on external current

drive strength and limit the node capacitance (minimize the wire, stub, connector and

trace length) to get the desired operation frequency result.

PCA9306

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9.3 — 14 November 2022

13 / 38

PCA9306DC1/DG Datasheet(PDF) 13 Page - NXP Semiconductors