S12ECT16B8CV2 datasheet(2/152 Pages) NXP

2 / 152 page

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or

design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;

neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,

or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was

negligent regarding the design or manufacture of the part.

DOCUMENT NUMBER

9S12XDP512DGV1/D

Revision History

Version

Number

Revision

Date

Effective

Date

Author

Description of Changes

V01.00

02 Jun 03

Initial Version

V01.01

22. Jul 03

•

Moved EWAIT function to PK7

•

Added ECLKX2 function to PE7

•

Moved TAGHI input to PE6

•

Moved TAGLO input to PE5

•

Corrected typo in figure 1-2

•

Added Freeze Mode to section 4

•

Modified PLL electrical parameters to TBD

•

Added four seperate interrupt vectors for PIT

•

Removed Regulator Current and Output Voltage Core and

Output Voltage PLL from Table 27-2

•

NVM Timing Characteristics Table A-11 maximum

fNVMOSC = 80MHz

•

Modified ATD Operating Characteristics Table A-8 and

A-9 to TBD

•

SPI Timing Characteristics set to TBD

V01.02

16.Aug 03

•

Added XSRAM20K control register to memory map

•

Added XSRAM20K interrupt vector

•

Included XSRAM20K Block Guide

•

Added XGATE Software Trigger to Table 5-1

•

Added section 4.2.5 Register visibility in Emulation and

Expanded modes

V01.03

23. Aug

•

Removed BDLC from Table 5-1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

S12ECT16B8CV2 Datasheet(PDF) 2 Page - NXP Semiconductors

S12ECT16B8CV2 Datasheet(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL