S12ECT16B8CV2 datasheet(88/152 Pages) NXP

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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12

The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies

to be supported:

•

the on chip phase Locked Loop (PLL)

•

the pll self clocking

•

the Oscillator

The clock generated by the PLL or Oscillator provides the main system clock frequencies Core Clock and

Bus Clock. As shown in Figure 3-1 this system clocks are used throughout the MCU to drive the Core,

the memories and the peripherals.

The Program Flash memory and the EEPROM are supplied by the Bus Clock and the Oscillator clock.The

Oscillator clock is used as a time base to derive the program and erase times for the NVM’s. Consult the

FTX512k4 block guide and the EETX4K block guide for more details on the operation of the NVM’s.

The CAN modules may be configured to have their clock sources derived either from the bus clock or

directly from the Oscillator clock. This allows the user to select its clock based on the required jitter

performance. Consult MSCAN block description for more details on the operation and configuration of

the CAN blocks.

The frequency generated by the PLL is determined by the two registers REFDIV and SYNR.

Please note that it is possible to configure the PLL to generate a system frequency

higher than that supported by the design of the device. It is the responsibility of the

user to insure that the device is operated within it’s specified limits at all time.

In order to ensure the presence of the clock the MCU includes an on-chip Clock Monitor connected to the

output of the Oscillator. The Clock Monitor can be configured to invoke the PLL self clocking mode or to

generate a system reset if it is allowed to time out as a result of no oscillator clock being present.

In addition to the clock monitor the MCU also provides a clock quality checker which performs a more

accurate check of the clock. The clock quality checker counts a predetermined number of clock edges

within a defined time window to insure that the clock is running. The checker can be invoked following

specific events such as on wake-up or clock monitor failure.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

S12ECT16B8CV2 Datasheet(PDF) 88 Page - NXP Semiconductors