S12ECT16B8CV2 datasheet(92/152 Pages) NXP

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MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12

4.3 Security

The MCU security feature allows the the protection of the on chip Flash and EEPROM memory. For a

detailed description of the security features refer to the S12X9SEC block guide.

4.4 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block Guide for

information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of

information about the clock system is the Clock and Reset Generator Block Guide (CRG).

4.4.1 Stop Mode

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static

mode. Wake up from this mode can be done via reset or external interrupts.

4.4.2 Pseudo Stop Mode

This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running

and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are

turned off. This mode consumes more current than the full STOP mode, but the wake up time from this

mode is significantly shorter.

4.4.3 Wait Mode

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute

instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.

For further power consumption the peripherals can individually turn off their local clocks.

4.4.4 Run Mode

Although this is not a low power mode, unused peripheral modules should not be enabled in order to save

power.

MISC/$0013

MMC

RI/WI

RE/WG

RI/WI

RE/WG

RI/WI

PORTK/$0032

PIM

RI/WI

RE/WG

RI/WI

RE/WG

RI/WI

DDRK/$0033

PIM

RI/WI

RE/WG

RI/WI

RE/WG

RI/WI

Table 4-6 Register Accessibility of Port Replacement Registers (PRR)

Single Chip modes

Expanded Modes

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

S12ECT16B8CV2 Datasheet(PDF) 92 Page - NXP Semiconductors

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