S12ECT16B8CV2 datasheet(90/152 Pages) NXP

90 / 152 page

MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12

The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of

the RESET signal in Emulation Expanded Mode, Emulation Single Chip Mode and Normal Expanded

Mode.(Table 4-2) The state of the EROMCTL pin is latched into the EROMON bit in the MISC register

on the rising edge of the RESET signal in Emulation Expanded Mode or Emulation Single Chip

Mode(Table 4-4).

Table 4-3 EROMON Pin Control Function

4.2.3 Oscillator Configuration Pin Control

At reset the configuration of the Oscillator can be selected using the XCLKS pin. The state of this pin on

the rising edge of the RESET pin determines which oscillator will be used.

Table 4-2 ROMON Pin Control Function

Mode

PK7 = ROMCTL

ROMON Bit

Special Single Chip Mode

Emulation Expanded Mode

Special Test Mode

Emulation Single Chip Mode

Normal Single Chip Mode

Normal Expanded Mode

Mode

PE3 = EROMCTL

EROMON Bit

Special Single Chip Mode

Emulation Expanded Mode

Special Test Mode

Emulation Single Chip Mode

Normal Single Chip Mode

Normal Expanded Mode

Table 4-4 Clock Selection Based on PE7

PE7 = XCLKS

Description

Full swing pierce oscillator or external clock source selected

Loop controlled pierce oscillator selected

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

S12ECT16B8CV2 Datasheet(PDF) 90 Page - NXP Semiconductors