DSP56300FMSLASHAD datasheet(13/120 Pages) NXP

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1-7

External Memory Expansion Port (Port A)

Output

(deasserted)

Bus Request

Asserted when the DSP requests bus mastership and

deasserted when the DSP no longer needs the bus. BR can be

asserted or deasserted independently of whether the DSP56305

is a bus master or a bus slave. Bus “parking” allows BR to be

deasserted even though the DSP56305 is the bus master (see

the description of bus “parking” in the BB signal description). The

Bus Request Hole (BRH) bit in the BCR allows BR to be

asserted under software control, even though the DSP does not

need the bus. BR is typically sent to an external bus arbitrator

that controls the priority, parking and tenure of each master on

the same external bus. BR is affected only by DSP requests for

the external bus, never for the internal bus. During hardware

reset, BR is deasserted and the arbitration is reset to the bus

slave state.

Input

Ignored Input

Bus Grant

Must be asserted/deasserted synchronous to CLKOUT for

proper operation. An external bus arbitration circuit asserts BG

when the DSP56305 becomes the next bus master. When BG is

asserted, the DSP56305 must wait until BB is deasserted before

taking bus mastership. When BG is deasserted, bus mastership

is typically given up at the end of the current bus cycle. This may

occur in the middle of an instruction that requires more than one

external bus cycle for execution.

Input/

Output

Input

Bus Busy

Indicates that the bus is active and must be asserted and

deasserted synchronous to CLKOUT. Only after BB is

deasserted can the pending bus master become the bus master

(and then assert the signal again). The bus master can keep BB

asserted after ceasing bus activity, regardless of whether BR is

asserted or deasserted. This is called “bus parking” and allows

the current bus master to reuse the bus without re-arbitration

until another device requires the bus. BB is deasserted by an

“active pull-up” method (that is, BB is driven high and then

released and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

Output

Driven high

(deasserted)

Bus Lock—BL is asserted at the start of an external divisible

Read-Modify-Write (RMW) bus cycle, remains asserted between

the read and write cycles, and is deasserted at the end of the

write bus cycle. This provides an “early bus start” signal for the

bus controller. BL may be used to “resource lock” an external

multi-port memory for secure semaphore updates. Early

deassertion provides an “early bus end” signal useful for external

bus control. If the external bus is not used during an instruction

cycle, BL remains deasserted until the next external indivisible

RMW cycle. The only instructions that assert BL automatically

are the BSET, CLR, and BCHG instructions when they are used

to modify external memory. An operation can also assert BL by

setting the BLH bit in the Bus Control Register.

Table 1-8. External Bus Control Signals (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56300FM/AD Datasheet(PDF) 13 Page - NXP Semiconductors

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