DSP56300FMSLASHAD datasheet(2/120 Pages) NXP

2 / 120 page

Table of Contents

DSP56305 Features ............................................................................................................................................ iii

Product Documentation........................................................................................................................................v

Chapter 1

Signal/ Connection Descriptions

1.1

Signal Groupings.............................................................................................................................................. 1-1

1.2

Power................................................................................................................................................................ 1-4

1.3

Ground.............................................................................................................................................................. 1-4

1.4

Clock ................................................................................................................................................................ 1-4

1.5

Phase Lock Loop (PLL) ................................................................................................................................... 1-5

1.6

External Memory Expansion Port (Port A)...................................................................................................... 1-5

1.7

Interrupt and Mode Control ............................................................................................................................. 1-8

1.8

Host Interface (HI32) ..................................................................................................................................... 1-10

1.9

Enhanced Synchronous Serial Interface 0 (ESSI0)........................................................................................ 1-18

1.10

Enhanced Synchronous Serial Interface 1 (ESSI1)........................................................................................ 1-20

1.11

Serial Communication Interface (SCI)........................................................................................................... 1-22

1.12

Timers............................................................................................................................................................. 1-23

1.13

JTAG/OnCE Interface .................................................................................................................................... 1-24

Chapter 2

Specifications

2.1

Introduction ...................................................................................................................................................... 2-1

2.2

Maximum Ratings ............................................................................................................................................ 2-1

2.4

Thermal Characteristics ................................................................................................................................... 2-2

2.5

DC Electrical Characteristics ........................................................................................................................... 2-3

2.6

AC Electrical Characteristics ........................................................................................................................... 2-4

Chapter 3

Packaging

3.1

Pin-Out and Package Information .................................................................................................................... 3-1

3.2

MAP-BGA Package Description ..................................................................................................................... 3-2

3.3

MAP-BGA Package Mechanical Drawing .................................................................................................... 3-13

Chapter 4

Design Considerations

4.1

Thermal Design Considerations ....................................................................................................................... 4-1

4.2

Electrical Design Considerations ..................................................................................................................... 4-2

4.3

Power Consumption Considerations ................................................................................................................ 4-3

4.4

PLL Performance Issues .................................................................................................................................. 4-4

4.5

Input (EXTAL) Jitter Requirements................................................................................................................. 4-5

Appendix A

Power Consumption Benchmark

Index

Data Sheet Conventions

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when

low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

True

Asserted

VIL/VOL

False

Deasserted

VIH/VOH

True

Asserted

VIH/VOH

False

Deasserted

VIL/VOL

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56300FM/AD Datasheet(PDF) 2 Page - NXP Semiconductors

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