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DSP56300FM/AD Datasheet(PDF) 4 Page - NXP Semiconductors |
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DSP56300FM/AD Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 120 page  iv On-Chip Memories • 192 K × 24-bit bootstrap ROM • 6144 K × 24-bit program ROM • 3072 K × 24-bit Y data ROM • Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: Off-Chip Memory Expansion • Data memory expansion to two 16 M × 24-bit word memory spaces in 24-Bit mode or two 64 K × 16-bit memory spaces in 16-Bit Compatibility mode • Program memory expansion to one 16 M × 24-bit words memory space in 24-Bit mode or 64 K × 16-bit in 16-Bit Compatibility mode • External memory expansion port • Chip Select Logic for glueless interface to SRAMs • On-chip DRAM Controller for glueless interface to dynamic random access memory (DRAMs) Reduced Power Dissipation • Very low-power CMOS design • Wait and Stop low-power standby modes • Fully static design specified to operate down to 0 Hz (dc) • Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Packaging The DSP56305 is available in a 252-pin molded array process-ball grid array (MAP-BGA) package. Program RAM Size Instruction Cache Size X Data RAM Size Y Data RAM Size Instruction Cache Switch Mode 6656 × 24 bits 0 3840 × 24 bits 2048 × 24 bits disabled disabled 5632 × 24 bits 1024 × 24 bits 3840 × 24 bits 2048 × 24 bits enabled disabled 7680 × 24 bits 0 2816 × 24 bits 2048 × 24 bits disabled enabled 6656 × 24 bits 1024 × 24 bits 2816 × 24 bits 2048 × 24 bits enabled enabled Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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