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DSP56300FM/AD Datasheet(PDF) 11 Page - NXP Semiconductors

Part # DSP56300FM/AD
Description  24-Bit Digital Signal Processor
PDF  120 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

DSP56300FM/AD Datasheet(HTML) 11 Page - NXP Semiconductors

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1-5
Phase Lock Loop (PLL)
1.5 Phase Lock Loop (PLL)
1.6 External Memory Expansion Port (Port A)
Note:
When the DSP56305 enters a low-power stand-by mode (Stop or Wait), it releases bus
mastership and tri-states the relevant Port A signals: A[0–23], D[0–23], AA0/RAS0–AA3/RAS3,
RD
, WR, BB, CAS, BCLK, and BCLK. If hardware refresh of external DRAM is enabled, Port A
exits the Wait mode to allow the refresh to occur and then returns to the Wait mode.
1.6.1 External Address Bus
Table 1-5. Phase Lock Loop Signals
Signal
Name
Type
State
During
Reset
Signal Description
CLKOUT
Output
Chip-driven
Clock Output
Provides an output clock synchronized to the internal core clock
phase.
If the PLL is enabled and both the multiplication and division
factors equal one, then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the
frequency of EXTAL.
PCAP
Input
Input
PLL Capacitor
Connects an off-chip capacitor to the PLL filter. Connect one
capacitor terminal to PCAP and the other terminal to VCCP.
If the PLL is not used, PCAP can be tied to VCC, GND, or left
floating.
PINIT/NMI
Input
Input
PLL Initial/Non-Maskable Interrupt
During assertion of RESET, the value of PINIT/NMI is written into
the PLL Enable (PEN) bit of the PLL control register, determining
whether the PLL is enabled or disabled. After RESET
deassertion and during normal instruction processing, the
PINIT/NMI Schmitt-trigger input is a negative-edge-triggered
Non-Maskable Interrupt (NMI) request internally synchronized to
CLKOUT.
PINIT/NMI can tolerate 5 V.
Table 1-6. External Address Bus Signals
Signal
Name
Type
State
During
Reset
Signal Description
A[0–23]
Output
Tri-stated
Address Bus
When the DSP is the bus master, A[0–23] specify the address
for external program and data memory accesses. Otherwise, the
signals are tri-stated. To minimize power dissipation, A[0–23] do
not change state when external memory spaces are not being
accessed.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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