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DSP56300FM/AD Datasheet(PDF) 8 Page - NXP Semiconductors

Part # DSP56300FM/AD
Description  24-Bit Digital Signal Processor
PDF  120 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

DSP56300FM/AD Datasheet(HTML) 8 Page - NXP Semiconductors

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1-2
Signal Groupings
Figure 1-1. Signals Identified by Functional Group
DSP56305
24
24
External
Address Bus
External
Data Bus
External
Bus
Control
Extended Synchronous
Serial Interface Port 0
(ESSI0)2
Timers3
PLL
JTAG/OnCE
Port
Power Inputs:
PLL
Internal VCC
plane
A[0-23]
D[0-23]
AA[0–3]
RAS[0–3]
RD
WR
BS
TA
BR
BG
BB
BL
CAS
BCLK
BCLK
TCK
TDI
TDO
TMS
TRST
DE
CLKOUT
PCAP
PINIT/NMI
VCCP
VCC
44
Serial
Communications
Interface (SCI) Port
2
Grounds:
PLL
PLL
Internal GND
plane
GNDP
GNDP1
GND
36
Interrupt
/Mode
Control
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
Host
Interface
(HI32) Port
1
PCI Bus
RXD
TXD
SCLK
SC[00-02]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
52
3
EXTAL
XTAL
Clock
Extended
Synchronous Serial
Interface Port 1
(ESSI1)2
SC[10-12]
SCK1
SRD1
STD1
3
Universal
Bus
Port B
GPIO
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0-2]
PC3
PC4
PC5
Port D GPIO
PD[0-2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
See Figure 1-2 for a listing of the Host
Interface/Port B Signals
Notes:
1.
The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be
configured as GPIO signals (PB[0–23]).
2.
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D
GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3.
TIO[0–2] can be configured as GPIO signals.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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