DSP56300FMSLASHAD datasheet(39/120 Pages) NXP

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2-9

AC Electrical Characteristics

DMA Request Rate

•

Data read from HI32, ESSI, SCI

•

Data write to HI32, ESSI, SCI

•Timer

•IRQ, NMI (edge trigger)

× T

—

75.0

87.5

25.0

37.5

—

60.0

70.0

20.0

30.0

Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external

memory (DMA source) access address out valid

4.25

× T

C + 2.0

55.1

—

44.5

—

Notes:

When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent

multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast

interrupts. Long interrupts are recommended when using Level-sensitive mode.

This timing depends on several settings:

• For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17

= 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay

(Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not

recommended, and these specifications do not guarantee timings for that case.

• For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization

delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored).

• For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the PCTL

Bit 17 and Operating Mode Register Bit 6 settings.

• For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The

PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with

the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes count or

PLL lock procedure completion.

• PLC value for PLL disable is 0.

• The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66 MHz

= 62

µs). During the stabilization period, T

C, TH, and TL is not constant, and their width may vary, so timing may vary as well.

Periodically sampled and not 100 percent tested.

Value depends on clock source:

• For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is active

and valid.

• For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing reflects the

crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other

components connected to the oscillator and reflects worst case conditions.

• When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device

circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to

the shortest possible duration.

If PLL does not lose lock.

VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100°C, CL = 50 pF.

WS = number of wait states (measured in clock cycles, number of TC).

Use the expression to compute a maximum value.

Figure 2-3. Reset Timing

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

VIH

RESET

Reset Value

First Fetch

All Pins

A[0–23]

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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