DSP56300FMSLASHAD datasheet(38/120 Pages) NXP

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2-8

AC Electrical Characteristics

Delay from WR assertion to interrupt request deassertion for

level sensitive fast interrupts

•

DRAM for all WS7

•SRAM WS = 1

•SRAM WS = 2, 3

•SRAM WS

≥ 4

80 MHz:

(WS + 3.5)

× T

C – 12.4

100 MHz:

(WS + 3.5)

× T

C – 10.94

80 MHz:

(WS + 3.5)

× T

C – 12.4

100 MHz:

(WS + 3.5)

× T

C – 10.94

80 MHz:

(WS + 3)

× T

C – 12.4

100 MHz:

(WS + 3)

× T

C – 10.94

80 MHz:

(WS + 2.5)

× T

C – 12.4

100 MHz:

(WS + 2.5)

× T

C – 10.94

—

Note 8

—

Note 8

Synchronous interrupt setup time from IRQA, IRQB, IRQC,

IRQD, NMI assertion to the CLKOUT Transition 2

7.4

5.9

Synchronous interrupt delay time from the CLKOUT Transition

2 to the first external address output valid caused by the first

instruction fetch after coming out of Wait Processing state

•

Minimum

•

Maximum

8.25

× T

C + 1.0

24.75

× T

C + 5.0

116.6

—

314.4

83.5

—

252.5

Duration for IRQA assertion to recover from Stop state

7.4

—

5.9

—

Delay from IRQA assertion to fetch of first instruction (when

exiting Stop)2, 3

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (Operating Mode Register Bit 6 = 0)

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (Operating Mode Register Bit 6 = 1)

•

PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop

Delay)

PLC

× ET

C × PDF + (128 K −

PLC/2)

× T

PLC

× ET

C × PDF + (23.75 ±

0.5)

× T

(9.25 ± 0.5)

× TC

1.6

290.6 ns

109.4

17.0

15.4 ms

121.9

1.3

232.5

87.5

13.6

12.3

97.5

Duration of level sensitive IRQA assertion to ensure interrupt

service (when exiting Stop)

2, 3

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is enabled (Operating Mode Register Bit 6 = 0)

•

PLL is not active during Stop (PCTL Bit 17 = 0) and Stop

delay is not enabled (Operating Mode Register Bit 6 = 1)

•

PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop

delay)

PLC

× ET

C × PDF + (128K −

PLC/2)

× T

PLC

× ET

C × PDF +

(20.5

± 0.5) × T

5.5

× T

17.0

15.4

68.8

—

13.6

12.3

55.0

—

Interrupt Request Rate

•

HI32, ESSI, SCI, Timer

•DMA

•IRQ, NMI (edge trigger)

•IRQ, NMI (level trigger)

× T

—

150.0

100.0

150.0

—

120.0

80.0

120.0

Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)

No.

Characteristics

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56300FM/AD Datasheet(PDF) 38 Page - NXP Semiconductors

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