DSP56300FMSLASHAD datasheet(49/120 Pages) NXP

49 / 120 page

2-19

AC Electrical Characteristics

Table 2-11. DRAM Page Mode Timings, Four Wait States1, 2, 3

No.

Characteristics

Symbol

Expression

80 MHz

100 MHz

Unit

Min

Max

Min

Max

131

Page mode cycle time for two consecutive accesses of the

same direction

Page mode cycle time for mixed (read and write) accesses

tPC

× T

4.5

× T

62.5

56.2

—

50.0

45.0

—

132

CAS assertion to data valid (read)

tCAC

2.75

× T

C − 5.7

—

28.7

—

21.8

133

Column address valid to data valid (read)

tAA

3.75

× T

C − 5.7

—

41.2

—

31.8

134

CAS deassertion to data not valid (read hold time)

tOFF

0.0

—

0.0

—

135

Last CAS assertion to RAS deassertion

tRSH

3.5

× T

C − 4.0

39.8

—

31.0

—

136

Previous CAS deassertion to RAS deassertion

tRHCP

× T

C − 4.0

71.0

—

56.0

—

137

CAS assertion pulse width

tCAS

2.5

× T

C − 4.0

27.3

—

21.0

—

138

Last CAS deassertion to RAS assertion5

•

BRW[1–0] = 00

•

BRW[1–0] = 01

•

BRW[1–0] = 10

•

BRW[1–0] = 11

tCRP

Not supported

4.25

× T

C − 6.0

5.25

× T

C − 6.0

7.25

× T

C − 6.0

—

47.2

59.6

84.6

—

36.5

46.5

66.5

—

139

CAS deassertion pulse width

tCP

× T

C − 4.0

21.0

—

16.0

—

140

Column address valid to CAS assertion

tASC

TC − 4.0

8.5

—

6.0

—

141

CAS assertion to column address not valid

tCAH

3.5

× T

C − 4.0

39.8

—

31.0

—

142

Last column address valid to RAS deassertion

tRAL

× T

C − 4.0

58.5

—

46.0

—

143

WR deassertion to CAS assertion

tRCS

1.25

× T

C − 4.0

11.8

—

8.5

—

144

CAS deassertion to WR assertion

tRCH

1.25

× T

C – 3.7

11.9

—

8.8

—

145

CAS assertion to WR deassertion

tWCH

3.25

× T

C − 4.2

36.4

—

28.3

—

146

WR assertion pulse width

tWP

4.5

× T

C − 4.5

51.8

—

40.5

—

147

Last WR assertion to RAS deassertion

tRWL

4.75

× T

C − 4.3

55.1

—

43.2

—

148

WR assertion to CAS deassertion

tCWL

3.75

× T

C − 4.3

42.6

—

33.2

—

149

Data valid to CAS assertion (write)

tDS

0.5

× T

C – 4.8

1.5

—

0.2

—

150

CAS assertion to data not valid (write)

tDH

3.5

× T

C − 4.0

39.8

—

31.0

—

151

WR assertion to CAS assertion

tWCS

1.25

× T

C − 4.3

11.3

—

8.2

—

152

Last RD assertion to RAS deassertion

tROH

4.5

× T

C − 4.0

52.3

—

41.0

—

153

RD assertion to data valid

tGA

3.25

× T

C − 5.7

—

34.9

—

26.8

154

RD deassertion to data not valid6

tGZ

0.0

—

0.0

—

155

WR assertion to data active

0.75

× T

C – 1.5

7.9

—

6.0

—

156

WR deassertion to data high impedance

0.25

× T

—3.1

—2.5

Notes:

The number of wait states for Page mode access is specified in the DCR.

The refresh period is specified in the DCR.

The asynchronous delays specified in the expressions are valid for DSP56305.

All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals

× T

C for read-after-read or write-after-write sequences).

BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page

access. N/A = does not apply because 100 MHz requires a minimum of three wait states.

RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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