DSP56300FMSLASHAD datasheet(10/120 Pages) NXP

10 / 120 page

1-4

Power

1.2 Power

1.3 Ground

1.4 Clock

Table 1-2. Power Inputs

Power

Name

Description

VCCP

PLL Power

Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the VCC power rail.

VCC

Quiet Power

Isolated power for the internal processing logic. This input is tied externally to all other chip power

inputs except VCCP. The user must provide adequate external decoupling capacitors.

Table 1-3. Grounds

Ground

Name

Description

GNDP

PLL Ground

Ground dedicated for PLL use. The connection should be provided with an extremely

low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located

as close as possible to the chip package.

GNDP1

PLL Ground 1

Ground dedicated for PLL use. The connection should be provided with an extremely

low-impedance path to ground.

GND

Quiet Ground

Isolated ground for the internal processing logic. This connection is tied internally to all other chip

ground connections, except GNDP and GNDP1. The user must provide adequate external

decoupling capacitors.

Table 1-4. Clock Signals

Signal

Name

Type

State

During

Reset

Signal Description

EXTAL

Input

External Clock/Crystal Input

Interfaces the internal crystal oscillator input to an external

crystal or an external clock.

XTAL

Output

Chip-driven

Crystal Output

Connects the internal crystal oscillator output to an external

crystal. If an external clock is used, leave XTAL unconnected.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56300FM/AD Datasheet(PDF) 10 Page - NXP Semiconductors

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