DSP56300FMSLASHAD datasheet(25/120 Pages) NXP

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1-19

Enhanced Synchronous Serial Interface 0 (ESSI0)

SCK0

PC3

Input/Output

Input or

Output

Input

Serial Clock

Provides the serial bit rate clock for the ESSI interface for both

the transmitter and receiver in Synchronous modes, or the

transmitter only in Asynchronous modes.

Although an external serial clock can be independent of and

asynchronous to the DSP system clock, it must exceed the

minimum clock cycle time of 6 T (that is, the system clock

frequency must be at least three times the external ESSI clock

frequency). The ESSI needs at least three DSP phases inside

each half of the serial clock.

Port C 3

The default configuration following reset is GPIO. For PC3,

signal direction is controlled through PRR0. The signal can be

configured as an ESSI signal SCK0 through PCR0.

This input is 5 V tolerant.

SRD0

PC4

Input/Output

Input or

Output

Input

Serial Receive Data

Receives serial data and transfers the data to the ESSI receive

shift register. SRD0 is an input when data is being received.

Port C 4

The default configuration following reset is GPIO. For PC4,

signal direction is controlled through PRR0. The signal can be

configured as an ESSI signal SRD0 through PCR0.

This input is 5 V tolerant.

STD0

PC5

Input/Output

Input or

Output

Input

Serial Transmit Data

Transmits data from the serial transmit shift register. STD0 is an

output when data is being transmitted.

Port C 5

The default configuration following reset is GPIO. For PC5,

signal direction is controlled through PRR0. The signal can be

configured as an ESSI signal STD0 through PCR0.

This input is 5 V tolerant.

Table 1-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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