FS6408 datasheet(37/111 Pages) NXP

37 / 111 page

NXP Semiconductors

FS6407/FS6408

6.5.3

Reset error counter

The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is

incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage,

overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated.

The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from

reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from

reset and fail to deep reset and fail (Deep Fail-safe mode), where regulators are off, RSTB and FS0B are activated, and a power on reset

or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the

RSTB_err_FS bit in the INIT FSSM2 register (Table 70).

If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”.

If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”.

This configuration must be done during INIT FS phase.

The final value of the reset error counter is based on the intermediate configuration.

• RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 16). When reset error counter reaches 6, the device goes into deep reset and

fails.

• RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 17). When reset error counter reaches 2, the device goes into deep reset and

fails.

In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails.

Conditions leading to an increment of the RSTB error counter, and according to the product configuration are:

• Watchdog error counter = 6

• Watchdog refresh NOK during INIT phase or Watchdog timeout

• IO_23 error detection (FCCU)

• Undervoltage

• Overvoltage

• IO_1 FB_Core Delta

• FS0B shorted to VDD

•SPI DED

• Reset request by the SPI

• External reset

Conditions leading to a transition go to FS, according to the product configuration are:

• IO_01/IO_23/IO_45 error detection

• Undervoltage

• Overvoltage

• IO_1 FB_Core Delta

• Analog BIST fail

•SPI DED

• RSTB shorted to high

FS6408 Datasheet(PDF) 37 Page - NXP Semiconductors