HCS12 datasheet(2/126 Pages) NXP

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Device User Guide — 9S12KT256DGV1/D V01.09

Freescale Semiconductor

Revision History

Version

Number

Revision

Date

Author

Description of Changes

01.00

16 JUL 02

Original Version.

01.01

22 NOV 02

Change load cap value on VDD and VDDPLL.

Correct expanded bus timing from 20MHz to 25 MHz.

01.02

15 JAN 03

Move ATD interrupt vector from $ffd0 to $ffd2.

Change PWeh and tDSW parameter in external bus timing.

01.03

13 JUN 03

Expand to a K-Family SoC Guide and include 9S12KT256.

01.04

18 JUN 03

Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.

01.05

14 NOV 03

Changed to a Device User Guide and added Document number.

Updated Table A-17 Oscillator Characteristics.

Replaced XCLKS with PE7 for Clock Selection diagrams.

Added CTRL to Table 2-1 Signal Properties.

Replaced Burst programming with Row Programming in NVM

electricals.

Changed Digital logic to Internal Logic.

Added LRAE bootloader information.

Changed PWEL, PWEH, tDSW, tACCE, tNAD, tNAV, tRWV, tLSV, tNOV,

tP0V and tP1V in the external bus timing.

Added voltage regulator characteristics.

01.06

10 FEB 04

Updated Table A-7 3.3V I/O Characteristics.

01.07

13 MAY 04

Updated Table A-16 NVM Timing Characteristics.

Corrected A.6.1.2 Row Programming time tbwpgm equation

01.08

20 JUL 04

Expanded K-family to include 9S12KC128, 9S12KC64, 9S12KL128

and 9S12KL64.

01.09

9 SEP 04

Updated osciilator start up time and supply current characteristics.

Added ATDCTL0 and ATDCTL1 register bits to Sec 1.7.

HCS12 Datasheet(PDF) 2 Page - NXP Semiconductors

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