HCS12 datasheet(61/126 Pages) NXP

61 / 126 page

Device User Guide — 9S12KT256DGV1/D V01.09

Freescale Semiconductor

2.3.5 XFC — PLL Loop Filter Pin

PLL loop filter. Please ask your Motorola representative for the interactive application note to compute

PLL loop filter elements. Any current leakage on this pin must be avoided.

Figure 2-4 PLL Loop Filter Connections

2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin

The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug

communication. In MCU expanded modes of operation when instruction tagging is on, an input low on

this pin during the falling edge of E-clock tags the high half of the instruction word being read into the

instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is

latched to the MODC bit at the rising edge of RESET.

2.3.7 PAD[15:8] / AN[15:8] — Port AD Input Pins [15:8]

PAD15 - PAD8 are general purpose input pins and analog inputs of the single analog to digital converter

with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD15 -

PAD8 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels

(ATD1) on MC9S12KT256 and MC9S12KG256.

2.3.8 PAD[7:0] / AN[7:0] — Port AD Input Pins [7:0]

PAD7 - PAD0 are general purpose input pins and analog inputs of the single analog to digital converter

with 16 channels on MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). PAD7 -

PAD0 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels

(ATD0) on MC9S12KT256 and MC9S12KG256.

2.3.9 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are

used for the multiplexed external address and data bus.

MCU

XFC

VDDPLL

HCS12 Datasheet(PDF) 61 Page - NXP Semiconductors