HCS12 datasheet(60/126 Pages) NXP

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Device User Guide — 9S12KT256DGV1/D V01.09

Freescale Semiconductor

NOTE:

All VSS pins must be connected together in the application. Because fast signal

transitions place high, short-duration current demands on the power supply, use

bypass capacitors with high-frequency characteristics and place them as close to

the MCU as possible. Bypass requirements depend on MCU pin load.

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET — External Reset Pin

An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up

state, and an output when an internal MCU function causes a reset.

2.3.3 TEST — Test Pin

This input only pin is reserved for test.

NOTE:

The TEST pin must be tied to VSS in all applications.

2.3.4 VREGEN — Voltage Regulator Enable Pin

This input only pin enables or disables the on-chip voltage regulator.

VDDPLL

2.5 V

Provides operating voltage and ground for the Phased-Locked Loop.

This allows the supply voltage to the PLL to be bypassed

independently. Internal power and ground generated by internal

regulator.

VSSPLL

0 V

Mnemonic

Nominal

Voltage

Description

HCS12 Datasheet(PDF) 60 Page - NXP Semiconductors