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HCS12 Datasheet(PDF) 112 Page - NXP Semiconductors |
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HCS12 Datasheet(HTML) 112 Page - NXP Semiconductors |
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112 / 126 page ![]() Device User Guide — 9S12KT256DGV1/D V01.09 112 Freescale Semiconductor A.9 SPI A.9.1 Master Mode Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-22. Figure A-5 SPI Master Timing (CPHA = 0) SCK (OUTPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) SS1 (OUTPUT) 1 9 5 6 MSB IN2 BIT 6 . . . 1 LSB IN MSB OUT2 LSB OUT BIT 6 . . . 1 10 4 4 2 9 (CPOL = 0) (CPOL = 1) 3 11 12 1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. |
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