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HCS12 Datasheet(PDF) 118 Page - NXP Semiconductors |
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HCS12 Datasheet(HTML) 118 Page - NXP Semiconductors |
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118 / 126 page ![]() Device User Guide — 9S12KT256DGV1/D V01.09 118 Freescale Semiconductor Table A-24 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF Num C Rating Symbol Min Typ Max Unit 1 P Frequency of operation (E-clock) fo 0 25.0 1 2 P Cycle time tcyc 40 2 3 D Pulse width, E low PWEL 17 3 4 D Pulse width, E high1 PWEH 17 4 5 D Address delay time tAD 8 5 6 D Address valid time to E rise (PWEL–tAD) tAV 11 6 7 D Muxed address hold time tMAH 2 7 8 D Address hold to data valid tAHDS 7 8 9 D Data hold to address tDHA 2 9 10 D Read data setup time tDSR 13 10 11 D Read data hold time tDHR 0 11 12 D Write data delay time tDDW 7 12 13 D Write data hold time tDHW 2 13 14 D Write data setup time(1) (PWEH–tDDW) tDSW 10 14 15 D Address access time(1) (tcyc–tAD–tDSR) tACCA 19 15 16 D E high access time(1) (PWEH–tDSR) tACCE 4 16 17 D Non-multiplexed address delay time tNAD 7 17 18 D Non-muxed address valid to E rise (PWEL–tNAD) tNAV 10 18 19 D Non-multiplexed address hold time tNAH 2 19 20 D Chip select delay time tCSD 16 20 21 D Chip select access time(1) (tcyc–tCSD–tDSR) tACCS 11 21 22 D Chip select hold time tCSH 2 22 23 D Chip select negated time tCSN 8 23 24 D Read/write delay time tRWD 7 24 25 D Read/write valid time to E rise (PWEL–tRWD) tRWV 10 25 26 D Read/write hold time tRWH 2 26 27 D Low strobe delay time tLSD 7 27 28 D Low strobe valid time to E rise (PWEL–tLSD) tLSV 10 28 29 D Low strobe hold time tLSH 2 29 30 D NOACC strobe delay time tNOD 7 30 31 D NOACC valid time to E rise (PWEL–tLSD) tNOV 10 31 |
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