TW2866C datasheet(38/143 Pages) RENESAS

38 / 143 page

TW2866C

FN8253 Rev. 0.00

Page 38 of 143

February 3, 2012

RECORD OUTPUT

To record audio data, the TW2866 provides the digital serial audio data through the ACLKR, ASYNR and

ADATR pins. Sampling frequency comes from 256xfs,320xfs or 384xfs audio system clock setting. Even

though the standard I2S and DSP format can have only 2 audio data on left and right channel, the

TW2866 can provide an extended I2S and DSP format which can have 16 channel audio data through

ADATR pin. The R_MULTCH defines the number of audio data to be recorded by the ADATR pin. ASYNR

signal is always fs frequency rate. One ASYNR period is always equal to 256xACLKR clock length with

AIN5MD=0. Figure 26 shows the digital serial audio data organization for multi-channel audio.

1/fs

ASYNR

ACLKR

MSB

LSB

8/16bit

ADATR

(a) I2S Format

1/fs

ASYNR

ACLKR

ADATR

MSB

LSB

8/16bit

(b)

DSP Format

FIGURE 26. TIMING CHART OF MULTI-CHANNEL AUDIO RECORD

Table 7 shows the sequence of audio data to be recorded for each mode of the R_MULTCH register. The

sequences of 0 ~ F do not mean actual audio channel number but represent sequence only. The actual

audio channel should be assigned to sequence 0 ~ F by the R_SEQ_0 ~ R_SEQ_F register. When the

ADATM pin is used for record via the R_ADATM register, the audio sequence of ADATM is also shown in

Table 7.

TW2866C Datasheet(PDF) 38 Page - Renesas Technology Corp