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TW2866C Datasheet(PDF) 22 Page - Renesas Technology Corp |
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TW2866C Datasheet(HTML) 22 Page - Renesas Technology Corp |
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22 / 143 page  TW2866C FN8253 Rev. 0.00 Page 22 of 143 February 3, 2012 TWO CHANNEL ITU-R BT.656 TIME-MULTIPLEXED FORMAT WITH 54MHZ The TW2866 supports two channels ITU-R BT.656 time-multiplexed format with 54MHz that is useful to security application requiring two channel outputs through one channel video port. The CHMDn register enables the dual ITU-R BT.656 time-multiplexed format and the MAINCHn/SELCHn register selects channel output to be multiplexed with its own channel on each VD pins. To de-multiplex the time-multiplexed data in the back end chip, the channel ID can be inserted in the data stream using the CHID_MD register. Two kinds of channel ID format can be supported. One is horizontal blanking code with channel ID and the other is ITU-R BT.656 sync code with channel ID. Figure 10 illustrates the logical timing diagram in the case of CH1 and CH2 time-multiplexed output through CH1 video output port. Figure 11 and Figure 12 illustrate VDn[7:0]/CLKPOn/CLKNOn pin default timing with 54MHz/27MHz clock output mode. CLKPOn (27MHz) CH1 CH2 VD1_54M FF Y50 00 Cr50 00 Y51 XY Cb52 Cb0 Y52 Y0 Cr52 Cb0 Y53 Y1 Cb54 Cb2 Y54 Y2 Cr54 Cr2 Y55 Y3 Cb56 Cb4 Y56 Y4 Cr56 CLKNOn (27MHz) Y50 Cr50 Y51 Cb52 Y52 Cr52 Y53 Cb54 Y54 Cr54 Y55 Cb56 Y56 Cr56 FF 00 00 XY Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 FIGURE 10. TIMING DIAGRAM OF TWO CHANNEL TIME-MULTIPLEXED FORMAT CLKPOn (54MHz) MAINCHn SELCHn VDn[7:0] FF Y50 00 Cr50 00 Y51 XY Cb52 Cb0 Y52 CLKNOn (54MHz) Y50 Cr50 Y51 Cb52 Y52 FF 00 00 XY Cb0 FIGURE 11. PIN OUTPUT TIMING OF TWO CHANNEL TIME-MULTIPLEXED FORMAT WITH 54MHZ CLOCK. |
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