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TW2866C Datasheet(PDF) 27 Page - Renesas Technology Corp |
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TW2866C Datasheet(HTML) 27 Page - Renesas Technology Corp |
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27 / 143 page  TW2866C FN8253 Rev. 0.00 Page 27 of 143 February 3, 2012 TABLE 5. SHOWS THE SPECIAL FORMAT OF ITU-R BT. 656 EMBEDDED TIMING CODE AND CHANNEL ID CODE Condition 656 FVH Value SAV-EAV Code Field V-time H-time F V H First Second Third Fourth Ch1 Ch2 Ch3 Ch4 EVEN BLANK EAV 1 1 1 0xFF 0x00 0x00 0xF0 0xF1 0xF2 0xF3 EVEN BLANK SAV 1 1 0 0xFF 0x00 0x00 0xE0 0xE1 0xE2 0xE3 EVEN ACTIVE EAV 1 0 1 0xFF 0x00 0x00 0xD0 0xD1 0xD2 0xD3 EVEN ACTIVE SAV 1 0 0 0xFF 0x00 0x00 0xC0 0xC1 0xC2 0xC3 ODD BLANK EAV 0 1 1 0xFF 0x00 0x00 0xB0 0xB1 0xB2 0xB3 ODD BLANK SAV 0 1 0 0xFF 0x00 0x00 0xA0 0xA1 0xA2 0xA3 ODD ACTIVE EAV 0 0 1 0xFF 0x00 0x00 0x90 0x91 0x92 0x93 ODD ACTIVE SAV 0 0 0 0xFF 0x00 0x00 0x80 0x81 0x82 0x83 OUTPUT ENABLING ACT After power-up, the TW2866 registers have unknown values. The RSTB pin must be asserted and released to bring all registers to its default values. After reset, the TW2866 data outputs are tri-stated. The OE register should be written after reset to enable outputs desired. VIDEO OUTPUT CHANNEL SELECTION If CHMDn[1:0] in Reg0xCA is set to 0hex,MAINCHn[1:0] in Reg0xCD selects one number of Video Channels to be output on VDn[7:0] pin as Single Channel ITU-R BT.656(D1) Format output.If CHMDn[1:0] in Reg0xCA is set to 1hex,MAINCHn[1:0] in Reg0xCD and SELCHn[1:0] in Reg0xCC select two numbers of Video Channels to be output on VDn[7:0] pin as Two Channel ITU-R BT.656(D1) Time-multiplexed Format output.If CHMDn[1:0] in Reg0xCA is set to 2hex, Four Channel ITU-R BT.656(D1) Time-multiplexed Format is output on VDn[7:0] pin. EXTRA SYNC OUTPUT The additional timing information such as syncs and field flag are also supported through the MPP pins. The video output timing is illustrated in Figure 17 and Figure 18 TW2866 HS/VS/FLD output function is compatible to TW9907 Video decoder HSYNC/VSYNC/FIELD output function. Start of VS timing is controlled by VSHT register(V timing) and OVSDLY register(H timing).End of VS timing is controlled by OVSEND register(V Timing).Start of FLD timing is controlled by OFDLY register(V timing).Start of HS timing is controlled by HSBEGIN register and End of HS timing is controlled by HSEND register. |
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