TW2866C datasheet(74/143 Pages) RENESAS

74 / 143 page

TW2866C

FN8253 Rev. 0.00

Page 74 of 143

February 3, 2012

0X9A – HSEND

Bit

Function

R/W

Description

Reset

7-0

HSEND[10:3]

R/W

HSYNC End position Control Bit10-3.

0X9B – OVSDLY

Bit

Function

R/W

Description

Reset

7-0

OVSDLY

R/W

VSYNC Start position. Control H position on VSYNC start.

0X9C – OVSEND

Bit

Function

R/W

Description

Reset

HASYNC

R/W

1:the length of EAV to SAV is set up and fixed by HBLEN registers.

0:the length of SAV to EAV is set up and fixed by HACTIVE

registers.

6-4

OFDLY

R/W

FIELD output delay.

0h:0H line delay FIELD output.(601 mode only)

1h-6h: 1H-6H line delay FIELD output.

7h:Reserved.

VSMODE

R/W

1:VSYNC output is HACTIVE-VSYNC mode.

0:VSYNC output is HSYNC-VSYNC mode.

2-0

OVSEND

R/W

Line delay for VSYNC end position.

0X9D – HBLEN

Bit

Function

R/W

Description

Reset

7-0

HBLEN

R/W

These bits are effective when HASYNC bit is set to 1.These bits

set up the length of EAV to SAV code when HASYNC bit is

1.Normal value is (Total pixel per line – HACTIVE) value.

NTSC/PAL-M(60Hz): 8Ah(138dec)=858-720

PAL/SECAM(50Hz): 90h(144dec)=864-720

If Reg0x0E[3](ATRIG for CH1) is set to 0,this value changes into

8Ah or 90h at auto video format detection initial time

automatically according to CH1 video detection status.

90h

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