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TW2866C Datasheet(PDF) 66 Page - Renesas Technology Corp |
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TW2866C Datasheet(HTML) 66 Page - Renesas Technology Corp |
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66 / 143 page ![]() TW2866C FN8253 Rev. 0.00 Page 66 of 143 February 3, 2012 0XA4(CH1)/0XA5(CH2)/0XA6(CH3)/0XA7(CH4) – ID DETECTION CONTROL Bit Function R/W Description Reset 7-6 IDX R/W These two bits indicate which of the four lower 6-bit registers is currently being controlled. The write sequence is a two steps process unless the same register is written. A write of {ID,000000} selects one of the four registers to be written. A subsequent write will actually write into the register. 0 5-0 NSEN / SSEN / PSEN / WKTH R/W IDX = 0 controls the NTSC color carrier detection sensitivity (NSEN). IDX = 1 controls the SECAM ID detection sensitivity (SSEN). IDX = 2 controls the PAL ID detection sensitivity (PSEN). IDX = 3 controls the weak signal detection sensitivity (WKTH). 1A / 20 / 1C / 2A 0XC4(CH1)/0XC5(CH2)/0XC6(CH3)/0XC7(CH4) – H MONITOR Bit Function R/W Description Reset 7-0 HFREF R Horizontal line frequency indicator(Test purpose only) X 0X80 – SOFTWARE RESET CONTROL REGISTER Bit Function R/W Description Reset 7-6 Reserved R Reserved 00b 5 AUDIORST W An 1 written to this bit resets the Audio portion to its default state but all register content remain unchanged. This bit is self- resetting. 0 4 VOUTRST W An 1 written to this bit resets Video data mux output logic to its default state but all register content remain unchanged. This bit is self-resetting. 0 3 VDEC4RST W An 1 written to this bit resets the Video4 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 2 VDEC3RST W An 1 written to this bit resets the Video3 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 1 VDEC2RST W An 1 written to this bit resets the Video2 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 0 VDEC1RST W An 1 written to this bit resets the Video1 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 |
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