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TW2866C Datasheet(PDF) 25 Page - Renesas Technology Corp |
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TW2866C Datasheet(HTML) 25 Page - Renesas Technology Corp |
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25 / 143 page  TW2866C FN8253 Rev. 0.00 Page 25 of 143 February 3, 2012 TABLE 4. THE CHANNEL ID FORMAT FOR 4 CH CIF TIME-MULTIPLEXED FORMAT WITH 54MHZ Condition 656 FVH Value SAV/EAV Code Sequence Field Vtime Htime F V H First Second Third Fourth Ch1 Ch2 Ch3 Ch4 EVEN Blank EAV 1 1 1 0xFF 0x00 0x00 0xF0 0xF1 0xF2 0xF3 EVEN Blank SAV 1 1 0 0xFF 0x00 0x00 0xE0 0xE1 0xE2 0xE3 EVEN Active EAV 1 0 1 0xFF 0x00 0x00 0xD0 0xD1 0xD2 0xD3 EVEN Active SAV 1 0 0 0xFF 0x00 0x00 0xC0 0xC1 0xC2 0xC3 ODD Blank EAV 0 1 1 0xFF 0x00 0x00 0xB0 0xB1 0xB2 0xB3 ODD Blank SAV 0 1 0 0xFF 0x00 0x00 0xA0 0xA1 0xA2 0xA3 ODD Active EAV 0 0 1 0xFF 0x00 0x00 0x90 0x91 0x92 0x93 ODD Active SAV 0 0 0 0xFF 0x00 0x00 0x80 0x81 0x82 0x83 (a) ITU-R BT.656 Sync Code with Channel ID Channel H Blanking Code with Channel ID Y Cb Cr Ch1 8’h10 8’h80 8’h80 Ch2 8’h11 8’h81 8’h81 Ch3 8’h12 8’h82 8’h82 Ch4 8’h13 8’h83 8’h83 (b) Horizontal Blanking Code with Channel ID FOUR CHANNEL D1 TIME-DIVISION-MULTIPLEXED FORMAT WITH 108MHZ Four channel of D1 (720x480) at 27MHz video stream that are time-division-multiplexed at 108MHz data rate format is implemented in TW2866 for security surveillance application. In order to reduce pin counts (thus shrink chip size) on both decoder’s digital output port and the input port of the back end compression Codec devices, TW2866 implements single 8 bit bus at 4 times the base band pixel clock rate of 27MHz. While quadrupling the data rate on a single bus to meet the new requirement, individually, each channel data arrangement still retains the base band 27MHz ITU-R BT.656 specification. For interface that can accept the new 108MHz clock bus, only one single clock at 108MHz is required. Embedded timing (SAV-EAV) code and Channel ID are inserted into each channel for de-multiplexing and separation of channel data. Ch4 Ch3 Ch2 Ch1 Legend Y10 Cr6 FF Cb0 Cr10 Y6 00 Y0 Y11 Cb8 00 Cr0 Y7 XY Y1 4xD1 Mux Data 108MHz Clock FIGURE 15. TIMING DIAGRAM OF 108MHZ 4 CH D1 TIME-DIVISION-MULTIPLEXED VIDEO DATA Figure 15 depicts the temporal arrangement of the video data in 108MHz data rate. Each channel is byte level time-division multiplexed (TDM). Main clock is 108MHz clock. |
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