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ADS5546

SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006

TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)

For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data

sheet.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Duty cycle of differential clock,

LVDS bit clock duty cycle

(CLKOUTP-CLKOUTM)

45%

50%

55%

≤ Fs ≤ 190 MSPS

Rise time measured from –50 mV to 50 mV

tr ,

Data rise time,

Fall time measured from 50 mV to –50 mV

100

200

Data fall time

≤ Fs ≤ 190 MSPS

Rise time measured from –50 mV to 50 mV

tCLKRISE,

Output clock rise time,

Fall time measured from 50 mV to –50 mV

100

200

tCLKFALL

Output clock fall time

≤ Fs ≤ 190 MSPS

Output enable (OE) to valid data

tOE

Time to valid data after OE becomes active

µs

delay

PARALLEL CMOS MODE

tsu

Data setup time (5)

Data valid(7) to 50% of CLKOUT rising edge

2.2

50% of CLKOUT rising edge to data becoming

Data hold time (5)

0.5

0.9

invalid(7)

Input clock rising edge zero-cross to 50% of

tPDI

Clock propagation delay

2.4

3.2

CLKOUT rising edge

Duty cycle of output clock (CLKOUT)

Output clock duty cycle

45%

≤ Fs ≤ 190 MSPS

Rise time measured from 20% to 80% of

DRVDD

tr,

Data rise time,

Fall time measured from 80% to 20% of

0.8

1.5

Data fall time

DRVDD

≤ Fs ≤ 190 MSPS

Rise time measured from 20% to 80% of

DRVDD

tCLKRISE,

Output clock rise time,

Fall time measured from 80% to 20% of

0.4

0.8

1.2

tCLKFALL

Output clock fall time

DRVDD

≤ Fs ≤ 190 MSPS

Output enable (OE) to valid data

tOE

Time to valid data after OE becomes active

delay

(7)

Data valid refers to logic high of 2 V and logic low of 0.8 V

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