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ADS5546 Datasheet(PDF) 17 Page - Texas Instruments

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Part # ADS5546
Description  14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
PDF  50 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5546 Datasheet(HTML) 17 Page - Texas Instruments

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ADS5546
SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
Table 8. Serial Interface Register Map (continued)
REGISTER ADDRESS
REGISTER DATA
DESCRIPTION
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
<GAIN> Gain programming - Channel gain can be programmed from 0 to 6 dB for SFDR/SNR trade-off. For each gain setting, the
input full-scale range has to be proportionally scaled. For 6 dB gain, the full-scale range will be 1 VPP compared to 2 VPP at 0 dB
gain.
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0 dB (Default after reset)
0
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
1 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
2 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
0
1
1
3 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
4 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
1
5 dB
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
6 dB
<LVDS CURRENT> – LVDS Output data and clock buffers nominal current programmability
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
3.5 mA (Default after reset)
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
2.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
4.5 mA
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1.75 mA
<CURRENT DOUBLE> – The output data and clock buffer currents are doubled from the value selected by the <LVDS CURRENT>
register.
value specified by <LVDS CURRENT>
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
(Default after reset)
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
2x data, 2x clock currents
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1x data, 2x clock currents
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2x data, 4x clock currents
<DATA TERM> Internal termination - Option to terminate the LVDS DATA buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination (Default after reset)
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
325
Ω
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
200
Ω
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
125
Ω
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
170
Ω
0
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
120
Ω
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
100
Ω
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
75
Ω
<CLK TERM> Internal termination - Option to terminate the LVDS CLK buffers inside the ADC to improve signal integrity. By
default, internal termination is disabled.
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
No termination (Default after reset)
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
325
Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
200
Ω
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
125
Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
170
Ω
0
1
1
1
1
1
1
0
0
0
0
1
0
1
0
0
120
Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
100
Ω
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
75
Ω
<CLKOUT POSN CMOS> – Output clock rising edge programmability in CMOS mode (1)
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
Default position
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
1
CLKOUT rising edge later by (1/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
1
CLKOUT rising edge later by (3/12)Ts
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
CLKOUT rising edge later by (2/12)Ts
(1)
Ts = 1/Sampling Frequency
17
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