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ADS5546 Datasheet(PDF) 16 Page - Texas Instruments

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Part # ADS5546
Description  14-BIT, 190 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
PDF  50 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS5546 Datasheet(HTML) 16 Page - Texas Instruments

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DESCRIPTION OF SERIAL REGISTERS
ADS5546
SLWS183C – NOVEMBER 2005 – REVISED OCTOBER 2006
Table 8 gives a summary of all the modes that can be programmed through the serial interface.
Table 8. Serial Interface Register Map
REGISTER ADDRESS
REGISTER DATA
DESCRIPTION
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
<STBY> – Global Power Down
NORMAL converter operation (Default after
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
reset)
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
STANDBY
<RST> – Software Reset
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
Resets all registers to default values
<DF> – Output Data Format
2's complement output format (Default after
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
reset)
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
Straight binary output format
<ODI> – Output Data Interface
DDR LVDS outputs (D4:D3 defaults to 00
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
after reset)
0
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
Parallel CMOS outputs
<REF> –Internal/External reference mode
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
Internal reference (Default after reset)
External reference – Force voltage on VCM
0
1
1
0
1
1
0
1
0
0
0
1
0
0
0
0
pin
<TEST PATTERN> – Output test pattern on data outputs
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Normal operation (Default after reset)
0
1
1
0
0
1
0
1
0
0
1
0
0
0
0
0
All zeros
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
All ones
Toggle pattern Alternate 1s and 0s on each
0
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
data output and across the data outputs.
Ramp pattern – Output data ramps from
0
1
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0x0000 to 0x3FFF every clock cycle
Custom pattern. Write the custom pattern in
0
1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
CUSTOM PATTERN registers A and B.
0
1
1
0
0
1
0
1
X
X
X
0
0
0
0
0
NOT USED
<CUSTOM PATTERN> – Output custom pattern on data outputs
0
1
1
0
1
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
CUSTOM PATTERN D7-D0
0
1
1
0
1
0
1
0
0
0
D13
D12
D11
D10
D9
D8
CUSTOM PATTERN D13-D8
<CLK GAIN> – Clock Buffer gain programmability, Gain decreases monotonically from Gain 4 to Gain 0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
0
Gain 4
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
Gain 3
0
1
1
0
1
0
1
1
0
0
1
0
0
1
1
0
Gain 2
0
1
1
0
1
0
1
1
0
0
1
0
0
0
0
0
Gain 1 (Default after reset)
0
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
Gain 0 Minimum gain
<POWER SCALING> Power scaling vs sampling frequency. The ADC can be operated at reduced power at lower sampling rates
with no loss in performance.
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
0
Default Fs > 150 MSPS (Default after reset)
0
1
1
0
1
1
0
1
1
0
1
0
0
0
0
0
Power Mode 1 – 105 < Fs
≤ 150 MSPS
0
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
Power Mode 2 – 50 < Fs
≤ 105 MSPS
0
1
1
0
1
1
0
1
1
1
1
0
0
0
0
0
Power Mode 3 – Fs
≤ 50 MSPS
16
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