13 / 66 page
AL103 Revision 1.0
9/00
Reference Only / Allayer Communications
13
PBA7
PBA6
PBA5
PBA4
PBA3
PBA2
PBA1
PBA0
235
236
237
238
240
241
242
243
O
SGRAM address line PBA0- PBA8 are sampled during the
ACTIVE command (row address) and READ/WRITE command
(column address with PBA8 defining auto precharge).
PBCS#
251
O
Chip Select. Enables and disables the command decoder of
the SGRAM.
PBRAS#
245
O
SGRAM Row Address Strobe.
PBCAS#
250
O
SGRAM Column Address Strobe.
PBWE#
249
O
Write Enable.
PBCLKI
195
O
System Clock Output to Drive the SGRAM.
Table 10: EEPROM Interface
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
EEDIO
252
I/O
EEPROM Serial Data Input and Output.
EECLK
253
O
EEPROM Serial Clock.
Table 11: MII PHY Management Interface
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
MDC
93
O
PHY Management Clock.
MDIO
94
I/O
PHY Management Data Input and Output.
Table 9: SGRAM Interface (Continued)
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