Electronic Components Datasheet Search
  English  ▼

X  

AL103 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

Part # AL103
Description  8 PORT LOW COST 10/100 SWITCH
PDF  66 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC2 [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC2 - List of Unclassifed Manufacturers

AL103 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

Back Button AL103 Datasheet HTML 3Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 4Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 5Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 6Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 7Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 8Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 9Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 10Page - List of Unclassifed Manufacturers AL103 Datasheet HTML 11Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 66 page
background image
AL103 Revision 1.0
9/00
Reference Only / Allayer Communications
7
2. Pin Descriptions
Table 1: MII Interface Port 0
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
M0TXD3
M0TXD2
M0TXD1
M0TXD0
7
8
9
11
O
Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
M0TXEN
12
O
Transmit Enable.
Synchronous to the transmit clock.
M0TXCLK
13
I
Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
M0RXD3
M0RXD2
M0RXD1
M0RXD0
21
19
18
17
I
Receive Data - NRZ data from the transceiver.
For MII interface, signal RX_DV, RX_ER and RX_D0 through
RX_D3 are sampled by the rising edge of RX_CLK.
M0RXDV
16
I
Receive Data Valid.
M0RXCLK
15
I
Receive Clock.
M0RXER
14
I
Receive Data Error.
M0CRS
3
I
Carrier Sense.
M0COL
5
I
Collision Detect.
Table 2: MII Interface Port 1
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
M1TXD3
M1TXD2
M1TXD1
M1TXD0
29
30
31
33
O
Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
M1TXEN
34
O
Transmit Enable.
Synchronous to the transmit clock.
M1TXCLK
35
I
Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com