AL103 Revision 1.0
9/00
Reference Only / Allayer Communications
9
Table 4: MII Interface Port 3
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
M3TXD3
M3TXD2
M3TXD1
M3TXD0
77
78
79
81
O
Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
M3TXEN
82
O
Transmit Enable.
Synchronous to the transmit clock.
M3TXCLK
83
I
Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
M3RXD3
M3RXD2
M3RXD1
M3RXD0
91
89
88
87
I
Receive Data - NRZ data from the transceiver.
For MII interface, signal RX_DV, RX_ER and RX_D0 through
RX_D3 are sampled by the rising edge of RX_CLK.
M3RXDV
86
I
Receive Data Valid.
M3RXCLK
85
I
Receive Clock.
M3RXER
84
I
Receive Data Error.
M3CRS
73
I
Carrier Sense.
M3COL
75
I
Collision Detect.
Table 5: MII Interface Port 4
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
M4TXD3
M4TXD2
M4TXD1
M4TXD0
105
106
107
109
O
Transmit Data - NRZ data to be transmitted to transceiver.
Signal TX_EN and TXD0 through TX_D3 are clocked out by
the rising edge of TX_CLK.
M4TXEN
110
O
Transmit Enable.
Synchronous to the transmit clock.
M4TXCLK
111
I
Transmit Clock Input.
25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
M4RXD3
M4RXD2
M4RXD1
M4RXD0
119
117
116
115
I
Receive Data - NRZ data from the transceiver.
For MII interface, signal RX_DV, RX_ER and RX_D0 through
RX_D3 are sampled by the rising edge of RX_CLK.
M4RXDV
114
I
Receive Data Valid.
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