 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LP5813 Datasheet(PDF) 8 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
LP5813 Datasheet(HTML) 8 Page - Texas Instruments |
|
|
8 / 60 page  Unless specified otherwise, typical characteristics apply over the full ambient temperature range (–40°C < TA < +85°C ), VIN = 3.6 V, VCC = 5 V, CIN = 1 μF, COUT = 1 μF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSD Thermal shutdown threshold for LED driver part TJ rising 150 °C TSD Thermal shutdown threshold for Boost converter part TJ rising 155 °C TSD_HYS Thermal shutdown hysteresis TJ falling below TSD 15 °C VLOD_TH LED open detection threshold Current set to 25.5 mA (max_current = 0, manual_dc_x = FFh) 70 90 110 mV VLOD_TH LED open detection threshold Current set to 51 mA (max_current = 1, manual_dc_x = FFh) 150 180 220 mV VLSD_TH LED short detection threshold lsd_th = 00h 0.32 × VOUT 0.35 × VOUT 0.38 × VOUT V lsd_th = 01h 0.42 × VOUT 0.45 × VOUT 0.48 × VOUT V lsd_th = 10h 0.52 × VOUT 0.55 × VOUT 0.58 × VOUT V lsd_th = 11h 0.62 × VOUT 0.65 × VOUT 0.68 × VOUT V 7.6 Timing Requirements Unless specified otherwise, typical characteristics apply over the full ambient temperature range (–40°C < TA < +85°C ), VIN = 3.6 V, VCC = 5 V, CIN = 1 μF, COUT = 1 μF. I2C Timing Requirements MIN NOM MAX UNIT Standard-mode fSCL SCL clock frequency 0 100 kHz tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU_STA Set-up time for a repeated START condition 4.7 µs tHD_DAT Data hold time 0 µs tSU_DAT Data set-up time 250 ns tr Rise time of both SDA and SCL signals 1000 ns tf Fall time of both SDA and SCL signals 300 ns tSU_STO Set-up time for STOP condition 4 µs tBUF Bus free time between a STOP and START condition 4.7 µs Cb Capacitive load for each bus line 400 pF Fast-mode fSCL SCL clock frequency 0 400 kHz tHD_STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU_STA Set-up time for a repeated START condition 0.6 µs tHD_DAT Data hold time 0 µs tSU_DAT Data set-up time 100 ns tr Rise time of both SDA and SCL signals 300 ns tf Fall time of both SDA and SCL signals 300 ns tSU_STO Set-up time for STOP condition 0.6 µs LP5813 SNVSC74 – SEPTEMBER 2023 www.ti.com 8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: LP5813 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
