LP5813 datasheet(27/60 Pages) TI

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9.5 Programming

The LP5813 is compatible with I2C standard specification. The device supports standard mode (100-kHz

maximum), fast mode (400-kHz maximum), and fast plus mode (1-MHz maximum). The device has 4 different

chip address versions, which allows connecting up to four parallel devices in one I2C bus.

I2C Data Transactions

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when clock signal is LOW. START and STOP conditions classify the beginning

and the end of the data transfer session. A START condition is defined as the SDA signal transitioning from

HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH

while SCL is HIGH. The bus leader always generates START and STOP conditions. The bus is considered to

be busy after a START condition and free after a STOP condition. During data transmission, the bus leader can

generate repeated START conditions. First START and repeated START conditions are functionally equivalent.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the leader. The leader releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge

after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the leader is the receiver, the receiver

must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte

clocked out of the follower. This negative acknowledge still includes the acknowledge clock pulse (generated by

the leader), but the SDA line is not pulled down.

I2C Data Format

The address and data bits are transmitted MSB first with 8-bits length format in each cycle. Each transmission

is started with Address Byte 1, which are divided into 5 bits of the chip address, 2 higher bits of the register

address, and 1 read/write bit. The other 8 lower bits of register address are put in Address Byte 2.The device

supports both independent mode and broadcast mode. The auto-increment feature allows writing / reading

several consecutive registers within one transmission. If not consecutive, a new transmission must be started.

The Bit 4 and Bit 3 are determined by the device, which can refer to Device Comparison.

Table 9-5. I2C Data Format

Address Byte1

Chip Address

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Independent

Bit 4

Bit 3

9th bit

8th bit

R: 1 W: 0

Broadcast

Address Byte2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

7th bit

6th bit

5th bit

4th bit

3rd bit

2nd bit

1st bit

0 bit

SCL

SDA

CA4

CA3

CA2

CA1

CA0

RA9

RA8

ACK

RA7

RA6

RA0

ACK

Address Byte 1

Address Byte 2

RA5

RA4

RA3

RA2

RA1

ACK

Start

Stop

Data Byte 1

Data Byte 2

Figure 9-22. I2C Write Timming

SCL

SDA

CA4

CA3

CA2

CA1

CA0

RA9

RA8

ACK

RA7

RA6

RA0

ACK

Address Byte 1

Address Byte 2

RA5

RA4

RA3

RA2

RA1

NACK

Start

Stop

Data Byte 2

CA4

CA3

CA2

CA1

CA0

RA9

RA8

ACK

Address Byte 1

Restart

Data Byte 1

Figure 9-23. I2C Read Timing

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LP5813

SNVSC74 – SEPTEMBER 2023

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