ATAM862 datasheet(78/110 Pages) ATMEL

78 / 110 page

4554E–4BMCU–05/06

ATAM862-3

Figure 23-21. MCL Bus Protocol 1

Bus not busy (1)

Both data and clock lines remain HIGH.

Start data transfer (2)

A HIGH to LOW transition of the SD line while the clock (SC)

is HIGH defines a START condition.

Stop data transfer (3)

A LOW to HIGH transition of the SD line while the clock (SC)

is HIGH defines a STOP condition.

Data valid (4)

The state of the data line represents valid data when,

after START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Acknowledge

All address and data words are serially transmitted to and

from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to

acknowledge word receipt.

Figure 23-22. MCL Bus Protocol 2

23.8.8

SSI Interrupt

The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit

buffer empty or receive buffer full), the end of SSI data telegram or on the falling edge of the

SC/SD pins on Port 4 (see “Port 4 Control Register (P4CR) Byte Write” on page 40). SSI inter-

rupt selection is performed by the Interrupt FunctioN control bit (IFN). The SSI interrupt is usually

used to synchronize the software control of the SSI and inform the controller of the present SSI

status. The Port 4 interrupts can be used together with the SSI or, if the SSI itself is not required,

as additional external interrupt sources. In either case this interrupt is capable of waking the con-

troller out of sleep mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Inter-

rupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in

P4CR register.

(2)

(1)

(4)

(3)

(1)

Start

condition

Data

valid

Data

change

Data

valid

Stop

condition

Start

n89

1st Bit

8th Bit

ACK

Stop

ATAM862 Datasheet(PDF) 78 Page - ATMEL Corporation

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