ATAM862 datasheet(15/110 Pages) ATMEL

15 / 110 page

4554E–4BMCU–05/06

ATAM862-3

15. MARC4 Architecture General Description

The microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripher-

als. The CPU is based on the Harvard architecture with physically separated program memory

(ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus

and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This

enhances program execution speed by allowing both instruction prefetching, and a simulta-

neous communication to the on-chip peripheral circuitry. The extremely powerful integrated

interrupt controller with associated eight prioritized interrupt levels supports fast and efficient

processing of hardware events. The microcontroller is designed for the high-level programming

language qFORTH. The core includes both an expression and a return stack. This architecture

enables high-level language programming without any loss of efficiency or code density.

Figure 15-1. Microcontroller Core

16. Components of Microcontroller Core

The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction

decoder and interrupt controller. The following sections describe each functional block in more

detail.

Instruction

decoder

CCR

TOS

ALU

RAM

Program

256 x 4-bit

MARC4 CORE

Clock

Reset

Sleep

Memory bus

I/O bus

Instruction

bus

Reset

System

clock

Interrupt

controller

On-chip peripheral modules

memory

ATAM862 Datasheet(PDF) 15 Page - ATMEL Corporation