ATAM862 datasheet(55/110 Pages) ATMEL

55 / 110 page

4554E–4BMCU–05/06

ATAM862-3

Table 22-9.

Timer 2 Mode Select Bits

22.12.3

Duty Cycle Generator

The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty

cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The

DCG-stage can also be used as additional programmable prescaler for Timer 2.

Figure 22-22. DCG Output Signals

22.12.4

Timer 2 Mode Register 2 (T2M2)

Address: "7"hex - Subaddress: "2"hex

Mode

T2MS1

T2MS0

Clock Output (POUT)

Timer 2 Modes

4-bit counter overflow (OVF1)

12-bit compare counter; the DCG

has to be bypassed in this mode

4-bit compare output (CM1)

8-bit compare counter with 4-bit

programmable prescaler and duty

cycle generator

4-bit compare output (CM1)

8-bit compare counter clocked by

SYSCL or the external clock input

T2I, 4-bit prescaler run, the

counter 2/1 starts after writing

mode 3

4-bit compare output (CM1)

8-bit compare counter clocked by

SYSCL or the external clock input

T2I, 4-bit prescaler stop and

resets

DCGIN

DCGO0

DCGO1

DCGO2

DCGO3

Bit 3Bit 2Bit 1Bit 0

T2TOP

T2OS2

T2OS1

T2OS0

Reset value: 1111b

T2TOP

Timer 2 Toggle Output Preset

This bit allows the programmer to preset the Timer 2 output T2O.

T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)

T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)

Note: If T2R = 1, no output preset is possible

T2OS2

Timer 2 Output Select bit 2

T2OS1

Timer 2 Output Select bit 1

T2OS0

Timer 2 Output Select bit 0

ATAM862 Datasheet(PDF) 55 Page - ATMEL Corporation

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