ATAM862 datasheet(54/110 Pages) ATMEL

54 / 110 page

4554E–4BMCU–05/06

ATAM862-3

22.12.1

Timer 2 Control Register (T2C)

Address: "7"hex - Subaddress: "0"hex

Table 22-7.

Timer 2 Clock Select Bits

22.12.2

Timer 2 Mode Register 1 (T2M1)

Address: "7"hex - Subaddress: "1"hex

Table 22-8.

Timer 2 Duty Cycle

Bit 3Bit 2Bit 1Bit 0

T2CS1

T2CS0

T2TS

T2R

Reset value: 0000b

T2CS1

Timer 2 Clock Select bit 1

T2CS0

Timer 2 Clock Select bit 0

T2CS1

T2CS0

Input Clock (CL 2/1) of Counter Stage 2/1

System clock (SYSCL)

Output signal of Timer 1 (T1OUT)

Internal shift clock of SSI (SCL)

Output signal of Timer 3 (TOG3)

T2TS

Timer 2 Toggle with Start

T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start

T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with

T2R

Timer 2 Run

T2R = 0, Timer 2 stop and reset

T2R = 1, Timer 2 run

Bit 3Bit 2Bit 1Bit 0

T2D1

T2D0

T2MS1

T2MS0

Reset value: 1111b

T2D1

Timer 2 Duty cycle bit 1

T2D0

Timer 2 Duty cycle bit 0

T2D1

T2D0

Function of Duty Cycle Generator (DCG)

Additional Divider Effect

Bypassed (DCGO0)

Duty cycle 1/1 (DCGO1)

Duty cycle 1/2 (DCGO2)

Duty cycle 1/3 (DCGO3)

T2MS1

Timer 2 Mode Select bit 1

T2MS0

Timer 2 Mode Select bit 0

ATAM862 Datasheet(PDF) 54 Page - ATMEL Corporation

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