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ATAM510 Datasheet(PDF) 49 Page - ATMEL Corporation |
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ATAM510 Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 72 page ![]() 49 4711B–4BMCU–01/05 ATAM510 Figure 3-21. Pulse Width Measurement 3.5.3.13 Phase Measurement Mode This mode allows the Timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the BP40 and BP41 pins (see Figure 3-22). The counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. This misalignment period is defined as the period during which BP40 is high and BP41 is low. Capturing and resetting of the counter always takes place on the rising edge of BP41. The measured value remains in the capture register until overwritten by the next measurement. Interrupts can be generated by either an overflow condition or an end-of- measurement (EOM) event. An EOM event signals to the CPU that a new measured value is present in the capture register and can be read, if required. Figure 3-22. Phase Measurement 3.5.3.14 Position Measurement Mode This mode is intended for the evaluation of positional sensors with bi-phase output signals. Fig- ure 3-23 on page 50 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. The direction can be deduced from the relative phase of the two signals. Therefore if BP40 is high on the rising edge of BP41, the moving mask travels to the left and if it is low then it travels to the right. The direc- tion (left/right) information is used to set the direction of the up/down counter which enables the BP40 pulses to be counted. Assuming that the system has been reset on a reference position, the counter will always hold the absolute current position of the moving mask. This can be read by the CPU if necessary. This mode is the only one in which the counter is allowed to decre- ment. Therefore, in this case it is possible for both an underflow or an overflow to occur. The overflow interrupt (if unmasked) will trigger on either of these conditions while the compare inter- rupt on the other hand will only trigger if the counter is counting upwards. To differentiate between an overflow or underflow, the compare value can be set to '0' hex, for example. An T0IN1 (BP41) t_low t_high "eom" Interrupt Captures and resets timer T0IN1 (BP41) T0IN0 (BP40) EOM Interrupt tp tp tp Captures and resets timer |
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