IMX7SCEC datasheet(6/155 Pages) NXP

6 / 155 page

i.MX 7Solo introduction

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 200 MHz in both

SDR and DDR modes, including HS200 and HS400 DDR modes

• USB:

— One high-speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY

— One high-speed USB 2.0 (480 Mbps) host with integrated HSIC USB (high-speed inter-chip

USB) PHY

• Miscellaneous IPs and interfaces:

— Three instances of SAI supporting up to three I2S and AC97 ports

— Seven UARTs, up to 4.0 Mbps:

– Providing RS232 interface

– Supporting 9-bit RS485 Multidrop mode

— Four eCSPI (Enhanced CSPI)

— Four I2C, supporting 400 kbps

— 1-gigabit Ethernet controller (designed to be compatible with IEEE Std 1588), 10/100/1000

Mbps with AVB support

— Four pulse width modulators (PWM)

— System JTAG controller (SJC)

— GPIO with interrupt capabilities

— 8x8 key pad port (KPP)

— One quad SPI

— Four watchdog timers (WDOG)

— One (12 x 12 mm) or two (19 x 19 mm) 2-channel, 12-bit analog-to-digital converters

(ADC)—effective number of bits (ENOB) can vary (typically 9–10 bits) depending on the

system implementation and the condition of the power/ground noise condition

The i.MX 7Solo family of processors integrates advanced power management unit and controllers:

• PMU (power-management unit), multiple LDO supplies, for on-chip resources

• Temperature sensor for monitoring the die temperature

• Software state retention and power gating for Arm and NEON

• Support for various levels of system power modes

• Flexible clock gating control scheme

The i.MX 7Solo family of processors uses dedicated hardware accelerators to meet the targeted

multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance

at low power consumption numbers, while having the CPU core relatively free for performing other tasks.

The i.MX 7Solo family of processors incorporates the following hardware accelerators:

• PXP—PiXel processing pipeline for imagine resize, rotation, overlay and CSC. Off loading key

pixel processing operations are required to support the LCD.

Security functions are implemented by the following hardware:

• Arm TrustZone technology including separation of interrupts and memory mapping

IMX7SCEC Datasheet(PDF) 6 Page - NXP Semiconductors