IMX7SCEC datasheet(9/155 Pages) NXP

9 / 155 page

Modules list

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Modules list

The i.MX 7Solo family of processors contains a variety of digital and analog modules. Table 2 describes

these modules in alphabetical order.

Table 2. i.MX 7Solo modules list

Block Mnemonic

Block Name

Subsystem

Brief Description

ADC1

ADC2

Analog to Digital

Converter

The ADC is a 12-bit general purpose analog to digital

converter (ADC2 is not available in the 12x12 package).

Arm

Arm Platform

Arm

The Arm Core Platform includes a Cortex-A7 core and

1x Cortex-M4. It also includes associated sub-blocks,

such as the Level 2 Cache Controller, SCU (Snoop

Control Unit), GIC (General Interrupt Controller),

private timers, watchdog, and CoreSight debug

modules.

BCH

Binary-BCH ECC

Processor

System control

peripherals

The BCH module provides up to 62-bit ECC

encryption/decryption for NAND Flash controller

(GPMI)

CAAM

Cryptographic

accelerator and

assurance module

Security

CAAM is a cryptographic accelerator and assurance

module. CAAM implements several encryption and

hashing functions, a run-time integrity checker, entropy

source generator, and a Pseudo Random Number

Generator (PRNG). The pseudo random number

generator is certifiable by Cryptographic Algorithm

Validation Program (CAVP) of National Institute of

Standards and Technology (NIST).

CAAM also implements a Secure Memory mechanism.

In i.MX 7Solo processors, the security memory

provided is 32 KB.

CCM

GPC

SRC

Clock Control Module,

General Power

Controller, System Reset

Controller

Clocks, resets, and

power control

These modules are responsible for clock and reset

distribution in the system, and also for the system

power management.

CSI

Parallel CSI

Multimedia

peripherals

The CSI IP provides parallel CSI standard camera

interface port. The CSI parallel data ports are up to 24

bits. It is designed to support 24-bit RGB888/YUV444,

CCIR656 video interface, 8-bit YCbCr, YUV or RGB,

and 8-bit/10-bit/16-bit Bayer data input.

CSU

Central Security Unit

security

The Central Security Unit (CSU) is responsible for

setting comprehensive security policy within the i.MX

7Solo platform.

DAP

Debug Access Port

System control

peripherals

The DAP provides real-time access for the debugger

without halting the core to access:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan

chains.

IMX7SCEC Datasheet(PDF) 9 Page - NXP Semiconductors

IMX7SCEC Datasheet(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL