CIRCC datasheet(25/70 Pages) SMSC

25 / 70 page

the Line Control/Status registers, and the Bus

Status register (Table 15). Typically, the controls

Block

Zero

are

used

during

Consumer IR message transactions.

Bits and

registers marked “reserved” in the table below

cannot be written and return 0s when read.

Programmers must set reserved bits to 0 when

writing to registers that contain reserved bits.

Table 15 - Register Block Zero

Address

Direction

Description

Default

R/W

Data Register

Interrupt Identification Register

‘00’hex

active

frame

eom

raw

mode

fifo

busy

reserved

R/W

Interrupt Enable Register

'00'hex

active

frame

eom

raw

mode

fifo

busy

reserved

Line Status Register (read)

'00'hex

under-

run

over-

run

frame

error

reserved

frame

abort

reserved

Line Status Address Register (write)

reserved

status register

address

R/W

Line Control Register A

'00'hex

fifo

reset

reserved

raw tx

raw rx

reserved

R/W

Line Control Register B

'00'hex

sce modes

bits

reserved

message count

Bus Status Register

'00'hex

not

empty

fifo

full

time-

out

reserved

valid

frame

Data Register (Address 0)

The Data Register is the FIFO access port.

Typically, the user will only write to the FIFO

when transmitting and read from the FIFO when

receiving. The host always has read access to

the FIFO regardless of the state of the SCE

Modes bits or the Loopback bit.

Host read

access to the FIFO is blocked when the FIFO is

empty. The host has write access to the FIFO

only when the Loopback bit is inactive and the

SCE Modes bits are zero or Transmit mode is

enabled.

Host write access to the FIFO is

blocked when the FIFO is full.

Interrupt Identification Register (Address 1)

When an interrupt is active the associated

interrupt identifier bit in the IID register is also

active regardless of the state of its individual

interrupt enable or the Master Interrupt Enable,

except for the FIFO Interrupt.

The Master

Interrupt Enable and the individual Interrupt

Enables serve only to enable the IID register

interrupts onto the Interrupt Request bus IRQ

shown in the Interface Description.

CIRCC Datasheet(PDF) 25 Page - SMSC Corporation

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