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CIRCC Datasheet(PDF) 54 Page - SMSC Corporation

Part # CIRCC
Description  Consumer Infrared Communications Controller
PDF  70 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

CIRCC Datasheet(HTML) 54 Page - SMSC Corporation

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54
SCE
The SCE is a half-duplex synchronous serial
communications controller that directs data flow
between the Bus Interface I/O block and the
Consumer IR (Remote Control) Encoder (Figure
20).
The
SCE
also
includes
partial
full-
duplex
loopback
functionality
for
diagnostic
testing.
Bit rates from .4kbps to 100kbps are
supported. All of the SCE register controls are
located in the nSCE-addressable 8-bit register
blocks.
FRAMING
The SCE operates with and without framing,
depending on the state of the FRAME bit in the
Consumer IR Remote Control register in SCE
Register Block Two. With framing implies that the
SCE works with the NEC Consumer IR decoder
so that the required portions of the frame
message can be extracted and placed in the 32
byte FIFO. Without framing implies that the SCE
operates simply as a serial-to-parallel converter
for
the
Consumer
IR
(Remote
Control)
encoder/decoder.
ACTIVE FRAME INDICATOR
The SCE signal nActiveFrame is a PLA state
variable that is synchronized to Consumer IR
message frames.
nActiveFrame is primarily
used to trigger active frame interrupts.
Transmit
nActiveFrame goes active as soon as the
Consumer IR transmitter starts modulating the
SCE data stream.
nActiveFrame becomes
inactive as soon as the transmit register is
empty.
Receive
When the
FRAME bit is zero, nActiveFrame
goes active as soon as the Consumer IR
receiver detects the first active bit-time of
infrared energy. nActiveFrame becomes inactive
whenever the Consumer IR receiver is manually
disabled, a DMA Terminal Count has occurred,
or following a FIFO Overrun.
When the FRAME bit is one, nActive Frame goes
active as soon as the NEC PPM frame format
decoder detects valid data following the leader
code. nActive Frame becomes inactive as soon
as the receiver updates the line status register
and signals an End-Of-Message following a FIFO
overrun.
Serial-to-Parallel
Converter
Parallel-to-Serial
Converter
8
1
8
1
Tim ing
&
Control
Transm it
Receive
Controls
CIR
Encoder
CIR
Decoder
FIGURE 20 - SCE BLOCK DIAGRAM



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