CIRCC datasheet(27/70 Pages) SMSC

27 / 70 page

FIFO Underrun, bit 7

The FIFO Underrun bit gets set to one when the

transmitter runs out of FIFO data.

FIFO Overrun, bit 6

The FIFO Overrun bit gets set to one when the

receiver tries to write data to the FIFO when the

FIFO Full flag is active.

Frame Error, bit 5

The Frame Error bit is set to one when bit-wide

violations are detected during the payload, i.e.

non-leader code, portion of NEC PPM remote

control message frames.

Frame Abort, bit 2

The Frame Abort bit is set to one following a

FIFO underrun during transmit, a FIFO Overrun

during receive, and when detected carriers are

out of range.

Status Register Address, bits 0 - 2 (write-

only)

Three Status Register Address bits control

software access to, and reside at the same

address as, the Line Status Registers.

The

Status Register Address bits are write-only and

occupy bits D0 to D2. To access any one of the

eight Line Status Registers first write the address

of the appropriate register (0 - 7), then read the

Line Control Register A (Address 4)

FIFO Reset, bit 7

When set to one, the FIFO Reset bit clears the

FIFO Full and Not Empty flags in the 32-byte

SCE FIFO. The FIFO Reset bit is automatically

set to zero following the re-initialization.

Raw Tx, bit 4

The Raw Tx bit controls the state of the infrared

emitter in Raw IR mode. The bit is read/write.

Raw Rx, bit 3

The Raw Rx bit represents the state of the

infrared detector in Raw IR mode.

The bit is

read-only.

CIRCC Datasheet(PDF) 27 Page - SMSC Corporation